1. Field of the Invention
This invention relates to amplifier circuits and more particular to offsets associated with amplifiers.
2. Description of the Related Art
FIG. 1 shows the block diagram of a typical high-speed optical receiver 100, designed to work at rates of, e.g., 2.7 GHz. The received optical energy 101 is converted to a current using a photodiode, 103. The photodiode signal current Io is converted to a voltage using the transimpedance amplifier (TIA) 105. The signal at the output of TIA 105 is small for low optical energy signals, and can contain significant corruption due to, e.g., noise and limited rise and fall times. The typical range of signal amplitude at the output of the TIA 105 is from a few millivolts to a few hundred millivolts. TIA 105 is followed by additional gain, usually implemented with a limit amplifier or an automatic gain control (AGC) amplifier 107. Note that although FIG. 1 shows a fully differential system, it is common for some of the illustrated signals, e.g., Io, V1, V2 or the clock and data outputs, to be single ended, and the principles described herein are still applicable.
The function of the limit amplifier is to produce a consistent waveform from the TIA output, which can be used by a clock and data recovery circuit (CDR) 109, irrespective of the incoming optical energy. The clock and data recovery circuit 109 recovers both the data and the clock typically embedded in the input data stream received by the photodiode D1 and provides differential clock and data signals 111 and 113, respectively.
If amplifier 107 is implemented as a limit amplifier, adequate gain is provided to create a full swing output from the minimum desired input signal. For larger input signals, the output does not increase significantly, however the output signal will be improved in regards to deterministic jitter and noise performance. If amplifier 107 is implemented as an AGC amplifier, the output signal strength is detected, and the gain is adjusted to provide optimal signal strength at the output for a wide range of input signal levels. In the case of a small input signal, the AGC gain will be large, comparable to the gain of a limit amplifier receiving a small signal in the same application. For larger signals, the AGC circuitry will reduce the gain to maintain the desired output signal strength, keeping the amplifier out of saturation. A larger signal will produce a better signal at the output of the AGC, since circuit non-idealities such as input-referred offset and noise become less significant.
FIGS. 2A shows exemplary output from the TIA amplifier 105. FIGS. 2B and 2C show respectively the expected outputs for a limit amplifier and an AGC amplifier for the input signal shown in 2A. FIG. 2B a shows that the limit amplifier is driven to the maximum output swing (+/xe2x88x920.5V). Though it preserves the data values and zero crossings, it does not preserve the shape of the input signals due to the non-linear limiting function. FIG. 2C shows that the AGC amplifier gain is set at a level to produce an output that is more linearly related to the input.
An AGC amplifier is implemented by detecting the signal strength at some point in the amplifier. This signal is used in a negative feedback loop to control the gain of the amplifier so that an optimal output signal is produced. Implementation of a high-speed AGC amplifier in a CMOS process presents many challenges. One reason for this is that a high quality diode is not readily available in a standard CMOS process. The diode facilitates rectification of the signal for amplitude detection. Though a similar function can be implemented using MOS devices, the circuit non-idealities and limited bandwidth of the devices make amplitude detection difficult. In a high speed bipolar process, accurate signal detection is feasible to provide the feedback signal for the AGC amplifier. Because the recovery of a bipolar device from an overdrive (saturation) can be slow, an AGC amplifier is more desirable for a bipolar process.
The limit amplifier or AGC amplifier often has two other functions associated with it: offset correction and slice level adjustment. An undesired offset in the amplifier can prevent the proper detection of small signals and random amplifier offsets, due to mismatch between critical devices, become greater with smaller device sizes. For a gigahertz CMOS limiting amplifier optimized for maximum gain and bandwidth, device sizes are relatively small and offsets on the order of the amplifier sensitivity (the minimum input peak to peak voltage) are not uncommon. That makes it necessary to include circuitry that senses the amplifier offset and cancels it. The offset correction is often implemented with the use of negative feedback from the amplifier""s output.
In some communication systems, such as those that operate in accordance with the Synchronous Optical Network (SONET) standard, scrambling and other techniques ensure that over the long term there will be a nearly equal amount of ones and zeros received by the data processing system. In such a system, desired offset correction can be implemented conceptually with the feedback system illustrated in FIG. 3. The offset is represented by the voltage Voff, which is shown as entering summing node 303. A sense circuit 301 detects any deviation from this equality, i.e., the amplifier offset. A trim circuit 305, which is coupled to summing node 307, can utilize the output of the sense circuit 301 to trim the offset.
Since the data equality holds only over a long period of time, the sensing circuitry should have a very low bandwidth. If not, the offset correction signal that is fed back can become a jitter mechanism. Many existing offset correction systems employ a purely analog approach, which makes realization of this low bandwidth only possible with large external passive devices. That results in extra pins on the integrated circuit being devoted to connecting these passive devices. However, the available number of pins can be limited on integrated circuits such as those implementing clock and data recovery circuits, and extra pins can result in bigger packages and thus bigger component costs. Not only do passive devices cost both board area and adversely affect component cost, their use brings a very sensitive node out of the chip, where great care should be taken to shield it from unwanted noise sources.
Another function that may be implemented by the amplifier stage 107 (see FIG. 1) is to provide an adjustable slicing level to compensate for the asymmetric noise characteristic present in the photodiode output. Slicing level is defined as the threshold voltage where an incoming signal is determined to be either a xe2x80x9c1xe2x80x9d bit or a xe2x80x9c0xe2x80x9d bit. The need for an adjustable slicing level can be seen by looking at the photodiode output current or the TIA output voltage shown in FIG. 2A. At low levels of optical energy (corresponding to a zero level bit for example), the noise current is low. At higher levels of optical energy (corresponding to a one-level bit), the noise current may be higher. This asymmetry, as shown in FIG. 2A, may require an introduction of an intentional offset to create the most reliable output. As shown in FIG. 2A, a slicing level of zero gives a smaller amount of margin for the positive swing compared to the negative swing. If the threshold is set to roughly xe2x88x922 mV in the case shown, the margin is more symmetric and better results are to be expected. Thus, introducing a small offset serves to optimize noise margin and signal strength. FIG. 4 illustrates the concept of introducing a slice voltage at summing node 401.
Some systems employ a closed-loop approach to dynamically adjust the slicing voltage. Some metric for system performance is monitored and the slicing voltage is adjusted accordingly. In this case, the amplifier offset is unimportant. Other systems may require that the slicing voltage remain at a fixed, repeatable level. Some solutions of this type of system provide the system designer with the means to monitor the output of the amplifier, allowing some feedback system to be designed off-chip which trims the slicing voltage to a desired level regardless of the amplifier offset. As in the offset correction example above, this requires large external components and exposes sensitive nodes to noise.
FIG. 5 shows a block diagram representation of a typical offset correction applied to either a limit amplifier or AGC amplifier in an optical system. For such a system it is assumed that the input signal has a zero average, and in the absence of amplifier offset, the output signal should have a zero average. In this configuration, the low pass filter H(s) 501 is used to find the output average value, and creates a negative feedback signal which is used to remove the output referred offset. One disadvantage of this arrangement is that if a non-zero threshold is set in the amplifier to implement an adjustable slicing function, the result of the offset correction loop will be to cancel out the slicing function. Capacitors 501 and 503 5 AC couple the input to the amplifier so that any DC conditions at the output of TIA 105 do not affect the amplifier. In this arrangement, if the TIA produces balanced differential output signals, the offset loop will only act on the amplifier offset. For unbalanced drive, or a DC coupled configuration, the offset loop will remove the combined offset of the incoming signal offset and the amplifier offset (if enough correction range is available).
In the case of an AGC amplifier, adjusting slice at the amplifier output can be acceptable, as there is a linear relationship between the input signal size and the output signal size, which can be roughly determined from parameters in the AGC control circuitry. But in the case of a limit amplifier, where the amplifier output is saturated for even the minimum desired input signal, a correction at the output cannot easily be related to the input signal size. Also, due to the large gain of the limit amplifier, adjusting the slice level at the output may not provide a large enough slice range when compared to the input signal.
The difficulties in implementing slice in a limit amplifier are greater when considering the gain variations that exist due to process and temperature variation. For this design, a single gain stage""s gain can vary roughly 2:1 over processing corners and the operating temperature range. For a n-stage topology, the total variation is roughly 2:1 to the nth power. For a six stage topology that is about a 64:1 range. The effect of the large gain uncertainty adds to the inaccuracies relating the slice level to the input signal, and the range of slice level available.
It would be desirable to achieve slice adjustment and offset correction without the offset correction canceling the slice adjustment. It would also be desirable to achieve slice adjustment and offset correction without the need for a large external capacitor to avoid the introduction of noise in sensitive nodes. Thus, it would be desirable for the entire solution to remain on-chip with no external components required. In addition, because of the limitations of available pins typical on clock and data recovery chips, it would be preferable if the entire solution requires as few pins as possible to help minimize pin count and therefore package size.
Accordingly, the invention provides a slice and offset solution that is entirely on chip by using a digital integrator in the feedback loop of the offset cancellation circuitry. When slicing is required, the amplifier offset is canceled and the specified slice level is introduced into the amplifier, allowing the system designer the flexibility of adjusting the slice level dynamically, or setting it to a fixed level. In the case of a fixed slice level, cancellation of the amplifier offset removes the need to program each system individuallyxe2x80x94an expensive manufacturing step. When slicing is not needed, the slice circuitry is turned off so as to minimize any power dissipation. In one embodiment only one pin (to program the slicing voltage) is utilized to minimize pin count and therefore package size. The elimination of external passive components saves board area, prevents introduction of undesirable noise at a sensitive node, and saves pins and package size.
In one embodiment the invention provides an integrated circuit that provides a slice and offset solution that includes an amplifier with a plurality of amplifier stages. An offset correction circuit detects an offset from one or more of the amplifier stages and includes a feedback loop that provides a feedback signal to the amplifier to correct the offset. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify a slice level of the amplifier to the feedback loop of the offset correction circuit so the feedback signal also incorporates the desired slice level.
In a preferred embodiment the feedback loop includes a low pass filter coupled to receive a combined signal indicative of the offset and the slice level. The low pass filter includes a digital integrator circuit supplying a digital value indicative of an integrated value of the combined signal. In one embodiment the digital integrator includes an up/down counter that counts in a direction determined according to a digital signal having a ones-density indicative of a value of the combined signal.
In another embodiment, the invention provides an integrated circuit that includes an amplifier, a slice circuit coupled to adjust a slice level of the amplifier, and an offset correction circuit including low pass filter implemented using a digital integrator coupled to correct an offset of the amplifier.
In still another embodiment, the invention provides a method of operating an amplifier having a plurality of amplifier stages. The method includes sensing an output of one stage of the amplifier to obtain a first offset signal that indicates if an undesired amplifier offset is present in one or more of the amplifier stages. In addition, a second offset signal is generated that indicates a desired amplifier offset. The first and second offset signals are combined to form a combined offset signal. A low pass filter operation is performed on the combined offset signal, which generates a feedback signal that is supplied to an input of a stage of the amplifier to thereby correct the undesired amplifier offset and introduce the desired amplifier offset into the amplifier. The low pass filter operation includes digitally integrating the combined signal.